Friday, November 5, 2010

New research on the SID ADSR

My previous post on the SID ADSR tables on the SID DIE left a question unanswered about the exact method by which the chip manages to apply the level changes in the envelopes at certain points in its decay/release stages.

Lucky for us, Frank Wolf took upon the challenge, and I'm quite priviledge to be allowed to publish his research on this blog.

So here is his analysis of that problem....

(high res)

6581 Envelope Generator (26.10.2010)
----------------------------------

In the upper part you can see the R-2R ladder; on the left is the MSB (Bit 7) of the 8 Bit counter.

Logarithmic Table
-----------------

Now take a look a the Table part! Here's the table in ASCII Form and reduced to the values on 'B' lines (please note the every second bit of the 8Bit counter is negated, i.e. the signal line is mirrored A<->B!)

B7 |B6 |B5 |B4 |B3 |B2 |B1 |B0  |Fixpoint|Signal line*
0   0   0   0   0   0   0   0     = 0x00    5
0   0   0   0   0   1   1   0     = 0x06    4
0   0   0   0   1   1   1   0     = 0x0E    3
0   0   0   1   1   0   1   0     = 0x1A    2
0   0   1   1   0   1   1   0     = 0x36    1
0   1   0   1   1   1   0   1     = 0x5D    0
1   1   1   1   1   1   1   1     = 0xFF    6

*The numbers of the signal lines have been chosen to match the numbers of the selector bits!

Every possible "Fixpoint" is compared to the 8 bit counter value keeping only one(!) of the seven signal lines "high" in case of equality. To be more exact: The lines are pulled down in case of inequality.
















The 5 selector bits for the logarithmic table are generated by feeding each of the the signal lines 0 to 4 into a simple flip-flop to "set" it. Output of the flip-flops is active "low"!) Additionally both adjacent signal lines are also fed into the flip-flip to "reset" it; resulting in a "high" level output.


Example:

Selector bit|
Signal line | "Reset" signal lines
0             1, 6
1             0, 2
2             1, 3
3             2, 4
4             3, 5

Sustain value
-------------

The 4 bits from the sustain value register are connected to:

Sustain bit 0 to Counter bit compare 0 + 4
Sustain bit 1 to Counter bit compare 1 + 5
Sustain bit 2 to Counter bit compare 2 + 6
Sustain bit 3 to Counter bit compare 3 + 7

So they are (as already known and verified through tests) compared like:

0x0 (S) == 0x00 (Cnt)
0x1 (S) == 0x11 (Cnt)
0x2 (S) == 0x22 (Cnt)
.
.
.
0xE (S) == 0xEE (Cnt)
0xF (S) == 0xFF (Cnt)